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| zilog w orldwide h eadquarters ? 910 e. h amilton a venue ? c ampbell , ca 95008 t elephone : 408.558.8500 ? f ax : 408.558.8300 ? i nternet : http :// www .z i log. com a dvanced p rogram b locking and ntsc l ine 21 xds d ecoder p reliminary p roduct s pecification ps000401-tvc0699 z86230
2 z86230preliminary ps000401-tvc0699 ?1999 by zilog, inc. all rights reserved. information in this publication concerning the devices, applica- tions, or technology described is intended to suggest possible uses and may be superseded. zilog, inc. does not assume liability for or provide a representation of accuracy of the information, devices, or technology described in this document. zilog also does not assume liability for intellectual property infringement related in any manner to use of information, devices, or technology described herein or otherwise. except with the express written approval of zilog, use of information, devices, or technology as critical components of life support systems is not authorized. no licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights. ps000401-tvc0699 z86230preliminary 3 t able of c ontents 1. a rchitectural o verview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1. b lock d iagram and o perational o verview . . . . . . . . . . . . . . . . . . . . 9 2. p in d escriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3. z86230 f eature s et . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1. vbi d ata p rocessing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2. s erial c ommunications i nterface . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3. s etup and o perational c ontrol . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4. s erial c ommunications i nterface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1. i 2 c b us o peration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5. c ommands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1. s erial p ort c ommands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2. read and write c ommands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.3. w riting to the z86230 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6. c ontrol r egisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.1. r egisters s ummary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.2. xds d ata r ecovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.3. z86230 c ommands and r egisters s ummary . . . . . . . . . . . . . . . . . . 38 6.4. p rogram b locking m ap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7. d emonstration p rograms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.1. c ommunicating with the z86230 . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.2. i 2 c o peration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.3. iico p rogram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.4. g eneral c ommands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.5. scripti p rogram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.6. s cript f iles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8. e lectrical c haracteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.1. a bsolute m aximum r atings 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.2. s tandard t est c onditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.3. dc c haracteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.4. ac and t iming c haracteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.5. e lectrical c haracteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9. a pplication i nformation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.1. r eference d esigns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10. p ackaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11. o rdering i nformation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.1. p art n umber d escription . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 12. p recharacterization p roduct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 c ustomer f eedback f orm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 z86230 p roduct s pecification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 c ustomer i nformation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 p roduct i nformation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 r eturn i nformation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 p roblem d escription or s uggestion . . . . . . . . . . . . . . . . . . . . . . . 56 4 z86230preliminary ps000401-tvc0699 ps000401-tvc0699 z86230preliminary 5 l ist of f igures f igure 1. v oltage /c ircuit r eference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 f igure 2. f unctional b lock d iagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 f igure 3. 18-p in dip and soic d evices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 f igure 4. i 2 c b us write (c ommand ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 f igure 5. i 2 c b us read (c ommand ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 f igure 6. i 2 c s erial t iming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 f igure 7. s tandard t est l oad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 f igure 8. z86230 r eference c ircuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 f igure 9. pcb d esign of z86230 r eference c ircuit . . . . . . . . . . . . . . . . . . 52 f igure 10. 18-l ead dip p ackage d iagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 f igure 11. 18-l ead soic p ackage d iagram . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6 z86230preliminary ps000401-tvc0699 ps000401-tvc0699 z86230preliminary 7 l ist of t ables t able 1. p in d escriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 t able 2. z86230 s erial c ontrol s ignals . . . . . . . . . . . . . . . . . . . . . . . . . . 16 t able 3. u ser p rogrammable f eatures . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 t able 4. z86230 i 2 c s lave a ddresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 t able 5. z86230 i 2 c read b ank s elect (rbs) c ommand . . . . . . . . . . . . 20 t able 6. i 2 c s erial t iming m in /m ax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 t able 7. b asic s erial c ommands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 t able 8. rds1Cread o ne b yte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 t able 9. rsd2Cr ead t wo b ytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 t able 10. wr xx Cw rite r egister xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 t able 11. s erial s tatus r egister . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 t able 12. c onfiguration r egister . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 t able 13. xds d ata a ctivity r egister . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 t able 14. xds f ilter r egister . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 t able 15. xds s econdary f ilter s ettings . . . . . . . . . . . . . . . . . . . . . . . . . 27 t able 16. i nterrupt r equest r egister . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 t able 17. i nterrupt m ask r egister . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 t able 18. c ontent a dvisory r atings s elect r egister 1 . . . . . . . . . . . . . . 28 t able 19. c ontent a dvisory r atings s elect r egister 2 . . . . . . . . . . . . . . 29 t able 20. c ontent a dvisory r atings s elect r egister 3 . . . . . . . . . . . . . . 30 t able 21. c ontent a dvisory r atings s elect r egister 4 . . . . . . . . . . . . . . 31 t able 22. c ontent a dvisory r egister 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 t able 23. c ontent a dvisory r egister 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 t able 24. b locking c ontrol r egister 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 t able 25. c ontent a dvisory r atings s elect r egister 5 . . . . . . . . . . . . . . 32 t able 26. c ontent a dvisory r atings s elect r egister 6 . . . . . . . . . . . . . . 34 t able 27. b locking c ontrol r egister 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 t able 28. xds d ata e xtraction e xample f ilter s ettings . . . . . . . . . . . . . 36 t able 29. z86230 s ummary of c ontrol c ommands . . . . . . . . . . . . . . . . . . 38 t able 30. s ummary of z86230 i nternal r egisters . . . . . . . . . . . . . . . . . . 39 t able 31. mpaa m atrix (u se c ontent a dvisory r ating r egister . . . . . . 40 t able 32. tv p arental g uidelines m atrix . . . . . . . . . . . . . . . . . . . . . . . . . 40 t able 33. c anadian e nglish m atrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 t able 34. c anadian f rench m atrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 t able 35. c onfiguration r egister s cript f iles . . . . . . . . . . . . . . . . . . . . . . 44 t able 36. dc c haracteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 t able 37. c omposite v ideo i nput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 t able 38. n on -s tandard v ideo s ignals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8 z86230preliminary ps000401-tvc0699 t able 39. hin/xin s ignal i nput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 t able 40. l ine 21 i nput p arameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 t able 41. r ecommended c omponent v alues r eference c ircuit . . . . . . . 51 b lock d iagram and o perational o verview a rchitectural o verview ps000401-tvc0699 z86230preliminary 9 1. architectural overview the z86230 is a stand-alone integrated circuit, capable of processing extended data services (xds) in field 2 of the vertical blanking interval (vbi) of a video frame. this device conforms to the transmission format de?ned in the television decoder circuits act of 1990, in accordance with the electronics industry associ- ation speci?cation eia-608a and eia-744a. the xds data is processed to provide either a program blocking signal (pb) or a recovered xds data packet. the pb matches the contents of the recovered con- tent advisory packet to the user selections input on the decoder. on-chip xds ?l- ters in the z86230 are fully-programmable, enabling recovery of only those xds data packets selected for use in tvs, vcrs, and set-top boxes. in addition, the z86230 is ideally suited to monitor picture-in-picture (pip) win- dow video for violence blocking and other xds data services. highlights of the z86230 include: 1. a stand-alone line 21 decoder for extended data services (xds). 2. extractable xds data from the input video. 3. full output of a selectable v-chip program blocking signal (pb). 4. selectable xds filter parameters from a list of preprogrammed values. 5. minimal communications and control overhead that provides simple implementation of violence blocking and auto clock set features. 6. full output of the recovered xds data through the i 2 c serial communication port. 7. two different slave addresses that are selectable in the i 2 c serial communication port. 8. selectable ntsc or pal operation. 1.1 b lock d iagram and o perational o verview the z86230 is designed to process xds data of the television vbi. the device requires both a composite video and a horizontal timing signal ( hin/xin input). several passive components are required for proper operation. commands are input to enable the decoder to process and control the v-chip response to the xds content advisory packet. the z86230 can also be con?gured to operate with pal video signals. in pal mode, the device decodes information encoded into vbi line 22. the encoded data must conform to the waveform and command structure de?ned for ntsc line 21 operation. figure 1 illustrates the functional block diagram of the z86230. a rchitectural o verview b lock d iagram and o perational o verview 10 z86230preliminary ps000401-tvc0699 f igure 1. f unctional b lock d iagram command processor address decoder ram buffer vw data slicer data clk recovery sliced data dual clamp lock stg sync slicer pg h lock few aw status reg test reg slice level cg logic ph1 ph2 fr & mux i dr & mux osc o/s control cg lines msync comp sync por ckt v/i ref addr bus serial control port msync data bus pb i 2 c sel nrst sclk sda video csync rref hin/xin lpf v dd v ss v ss (a) dclk data line dclk div c cir v lock line & field fld ls sfld sls control cclk cw line & fld dec msgr clk div comp h sel x out nc intro nc b lock d iagram and o perational o verview a rchitectural o verview ps000401-tvc0699 z86230preliminary 11 1.1.1 input signals the composite video input should be a signal which is nominally 1.0 volt p-p, with sync tips negative and band limited to 600 khz. the z86230 operates with an input level variation of 3 db. the hin/xin input signal is required to bring the voltage-controlled oscillator (vco) close to the required operating frequency. 1.1.2 video input signal processing the composite video input is ac-coupled to the device where the sync tip is internally clamped to a ?xed reference voltage. the data slicer extracts a clean cmos-level data signal by slicing the signal at its midpoint. the slice level is established on an adaptive basis during line 21. the sync slicer processes the clamped composite video signal to extract com- posite sync. this signal is used to lock the internal logic to the incoming video. the slice level is stored on the sync slice capacitor, csync . the data clock recovery circuit operates in conjunction with the horizontal (h) lock circuit. these circuits produce a data clock ( dclk ) and, when line 21 code appears, dclk phase lock is achieved during the clock run-in burst (used to reclock the sliced data). when phase lock is established, dclk is maintained until a change in the video signal occurs. 1.1.3 voltage-controlled oscillator (vco) and one-shot all internal timing and synchronizing signals are derived from the on-board 12- mhz vco. its output is the dclk signal used to drive the horizontal and vertical counter chains. the one-shot circuit produces a horizontal timing signal derived from the incom- ing video. the vco exhibits stable gain characteristics and good power supply rejection. 1.1.4 timing and counting circuits the dclk is divided to generate the horizontal timing signals h and 2h .the h signal is further divided in the line counter ( line cntr ) and ?eld counter ( fld cntr ) to produce the various decodes used to establish vertical lock and to time the control functions required for proper operation. 1.1.5 command processor the command processor controls the manipulation of the data for storage. during the recovery time, the command processor, in conjunction with the data recovery circuits, recovers the xds data. a rchitectural o verview b lock d iagram and o perational o verview 12 z86230preliminary ps000401-tvc0699 1.1.6 decoder control circuit the decoder control circuit block is the users communications port. this circuit converts the information from the control port into the internal control signals required to establish the operating mode of the decoder. the z86230 responds to its slave address for both the read and write condi- tions. if the read bit is low (indicating a write sequence), then the z86230 responds with an acknowledge. the master should then send an address byte fol- lowed by a data byte. if the read bit is high (indicating a read sequence), then the z86230 responds with an acknowledge followed sequentially by a status byte and a data byte. read data is only available through indirect addressing. write addressing exhibits both indirect and direct modes. the busy bit in the status byte indicates if the write operation is completed or if read data is available. 1.1.7 voltage/current reference the voltage/current reference circuit uses an externally connected resistor to establish the reference levels that are used throughout the z86230. for a minimal investment, the use of an external resistor can also provide improved internal pre- cision. f igure 2. v oltage /c ircuit r eference rref 10 k w 2% pin 10 gnd b lock d iagram and o perational o verview p in d escriptions ps000401-tvc0699 z86230preliminary 13 2. pin descriptions there are 2 different packages, 18-pin dip and 18-pin soic, available in the z86230. f igure 3. 18-p in dip and soic d evices t able 1. p in d escriptions symbol pin # function direction description i 2 c sel 1 i 2 c address select input selects i 2 c address. low(0) sets the slave address to 28h for write and 29h for read. high(1) sets the slave address to 2ah for write and 2bh for read. h sel 2 hin/xin select input selects the source of the horizontal frequency signal. tying pin 2 high(1) selects xin mode. tying pin 2 low(0) selects hin mode. x out 3 xtal output output when operating in xin mode this pin is the output pin for the xtal circuit. in hin mode, the x out pin is a no connect (nc). nrst 4 reset input capable of being tied to an reset signal if a power-on reset action is required. reset must be held low(0) for at least 100ns; otherwise, the pin must be tied high(1). 1 2 3 4 5 6 7 8 9 17 16 15 14 13 12 11 10 18 i 2 c sel h sel x out nrst hin/xin v ss video csync lpf nc intro nc sclk sda pb v dd v ss (a) rref z86230 dip/soic p in d escriptions b lock d iagram and o perational o verview 14 z86230preliminary ps000401-tvc0699 hin/xin 5 horizontal in/xtal in input when xtal mode is selected, the horizontal frequency signal may be generated on the chip using the external 32.768-khz crystal circuit, as shown below. this circuit must be connected between pin 5 and 3. when hin mode is selected, a horizontal frequency signal must be supplied to the pin. this signal must be within +3% fh; however, the frequency signal can exhibit any polarity and duty cycle. alternatively, an external horizontal frequency signal may be used in xin mode operation. in this case, the signal must exhibit a frequency of 32.768 khz. v ss 6 power supply (digital) gnd n/a this pin is the lowest potential power pin for the digital circuit that is typically tied to system ground. video 7 composite video input composite ntsc video input, 1.0v p-p (nom), band limited to 600 khz. the circuit operates with signal variation between 0.7C1.4v p-p. the polarity is sync tips negative. this signal pin should be ac-coupled through a 0.1 f capacitor and driven by a source impedance of 470 ohms or less. csync 8 composite sync output sync slice level. a 0.1 mf capacitor must be tied between this pin and analog ground v ss (a). this capacitor stores the sync slice level voltage. t able 1. p in d escriptions symbol pin # function direction description z86230 y1 32.768khz r1 22m r2 470k c1 10pf c2 20pf pin 5 pin 3 crystal type: 32.768 khz, cl=12.5pf series resistance < 35 kohms epson, c-001r 32.768 khz or fox, nc26, nc28 or equivalent (18 kohms typ) b lock d iagram and o perational o verview p in d escriptions ps000401-tvc0699 z86230preliminary 15 lpf 9 loop filter output loop filter. a series rc low-pass ?lter must be tied between this pin and analog ground v ss (a). there must also be second capacitor from the pin to v ss (a). rref 10 resistor reference input reference setting resistor. this resistor must be 10 kohms, 2%. v ss (a) 11 power supply (anlalog) gnd n/a this pin is the lowest potential power pin for the analog circuit that is typically tied to system ground. v dd 12 power supply +5v n/a the voltage on this pin is nominally 5.0 volts, and may range between 4.75 to 5.25 volts with respect to the v ss pins. pb 13 program blocking output this pin is high(1) when the received content advisory packet matches the viewers selection as entered into the content advisory rating select registers. sda 14 serial data in/output this pin is the bidirectional data line for sending and receiving serial data. sclk 15 serial clock input this pin acts as an input pin for the serial clock signal from the i 2 c master. the clock rate is expected to be within i 2 c limits. nc 16 no connect n/a no connect intro 17 interrupt output output this pin provides an interrupt signal to the master control device in accordance with the settings in the interrupt mask register. nc 18 no connect n/a no connect t able 1. p in d escriptions symbol pin # function direction description lpf csync c6 c5 c7 r5 8 9 z86230 f eature s et vbi d ata p rocessing 16 z86230preliminary ps000401-tvc0699 3. z86230 feature set the primary features of the z86230 are brie?y described below. more complete descriptions can be found in later sections of this document. 3.1 vbi d ata p rocessing the z86230 extracts the xds data in line 21 of the incoming video. processing includes: 1. extracting xds data from the input video. 2. outputting the v-chip program blocking signal (pb). 3. outputting the xds data through the serial port (raw or filtered). 4. selecting the xds filter parameters from a list of preprogrammed values. 5. selecting either ntsc or pal operation. 3.2 s erial c ommunications i nterface communications and control of the z86230 is possible through the i 2 c serial con- trol interface, composed of: 1. a 2-wire i 2 c interface. 2. two available slave addresses. t able 2. z86230 s erial c ontrol s ignals signal i 2 c sel sclk sda pin # 1 15 14 i/o i i i/o 1 st i 2 c address ( 28h (w)/ 29h (r)) 0 clk data 2 nd i 2 c address( 2ah (w)/ 2bh (r)) 1 clk data s etup and o perational c ontrol z86230 f eature s et ps000401-tvc0699 z86230preliminary 17 3.3 s etup and o perational c ontrol the z86230 is fully programmable through its ?exible i 2 c serial communication port. the following tables provide a partial list of user-programmable features and default conditions upon reset . t able 3. u ser p rogrammable f eatures feature parameters reset condition video standard ntsc/pal ntsc vco lock video/external hin video h lock video/external hin video xds data output raw/filtered off contents advisory rating select on/off off program blocking on/off on blocking no rating programs on/off off program unblock hold off up to 254 vertical frames 0 s erial c ommunications i nterface i 2 c b us o peration 18 z86230preliminary ps000401-tvc0699 4. serial communications interface commands and data are sent to and from the z86230 through its i 2 c serial com- munications interface. this port is the path for setting the con?guration and oper- ational modes of the device. the interface is also used as the port for outputting the recovered xds data. 4.1 i 2 c b us o peration the z86230 supports a bidirectional 2-wire bus and data transmission protocol. the bus is controlled by the master device, which generates the serial clock ( sclk ), controls the bus access, and generates the start and stop conditions. the serial data ( sda ) pin is the bidirectional data line. the z86230 is a slave device with two possible slave addresses. when the i 2 c sel pin is low, the slave address is 28h for write and 29h for read . when the i 2 c sel pin is high, the slave address is 2ah for write and 2bh for read . the z86230 can receive or transmit data under control of the master device. com- munication is initiated when the master device sends the start condition fol- lowed by the z86230 slave address read byte or slave address write byte. the z86230 responds with an acknowledge. the i 2 c rd / wr bit is the least signi?cant bit (lsb) of the i 2 c addresses listed below in table 4. 4.1.1 the i 2 c bus protocol the bus protocol requires that: 1. data transfer can only be started when the bus is not busy. 2. during data transfer, data transitions must not occur while the clock is high. 4.1.2 bus conditions bus conditions are de?ned as: not busy. data and clock lines are both high. start. a high-to-low transition of the sda line while the sclk line is high. stop. a low-to-high transition of the sda line while the sclk line is high. t able 4. z86230 i 2 c s lave a ddresses read write 1 st i 2 c address 29h 28h 2 nd i 2 c address 2bh 2ah n ote : low(0) on pin 1 selects the 1 st i 2 c address; high(1) on pin 1 selects the 2 nd i 2 c address. i 2 c b us o peration s erial c ommunications i nterface ps000401-tvc0699 z86230preliminary 19 acknowledge. when addressed, the receiving device must output an acknowl- edge after the reception of each byte. the master device must generate the clock for the acknowledge bit. acknowledge is sda = low . not acknowledge ( nack ) is sda = high . data. the data ( sda ) is output by the transmitting device on the falling edge of sclk , msb ?rst. the receiving device interprets the data, msb ?rst, on the rising edge of sclk . communication with the z86230 is initiated when the master device sends the z86230 slave address following a start condition. the z86230 has a preset, sin- gle, seven-bit slave address. the z86230 responds with an acknowledge. the eighth bit of the slave address is driven high for read operations and low for write operations. 4.1.3 writing to the i 2 c bus commands and data are written to the z86230 using the i 2 c bus interface. the device is enabled when an i 2 c start condition, followed by its slave address write byte, is received. a write operation is ended and the bus is disabled upon the receipt of an i 2 c stop condition. any number of command bytes, up to 32, may be sent after the device is write -enabled. each of these commands is either 1 or 2 bytes in length. the device executes the commands in order of receipt. over?owing the 32 byte buffer causes improper operation. the rdy bit of the serial status register ( ssr ) may be read to determine if there is room in the com- mand buffer for at least 2 bytes of command data. the status register data is out- put immediately following the receipt of the slave address read . the ?rst byte of a 2-byte command is always written ?rst. the masters sequence for writing a 2-byte command, followed by a 1-byte command is displayed in the following example: start slave_address_write/slave ack cmd1_write/slave ack data1_write/slave ack cmd2_write/slave ack stop s erial c ommunications i nterface i 2 c b us o peration 20 z86230preliminary ps000401-tvc0699 4.1.4 reading data using the i 2 c bus the z86230 i 2 c bus supports read sequences up to 34 bytes in length. all read sequences output the serial status register ( ssr ) as the ?rst output byte. the data to be read is selected by sending the read bank select ( rbs ) command. four read bank modes are available in the z86230: f igure 4. i 2 c b us write (c ommand ) n ote : the status register rdy bit must be read and checked prior to the start condition of either write sequence above. refer to the one byte read (status only) in figure 5 for more information on reading the status register. t able 5. z86230 i 2 c read b ank s elect (rbs) c ommand rbs command descriptions bank 0 a general-purpose bank used to read the z86230-de?ned internal registers. the register to be read from bank 0 is set up manually using the read select commands, rds1 and rds2. these commands load the selected data byte (or pair of bytes) into the ?rst location(s) of bank 0, and set the dav bit to indicate the availability of data. bank 1 a special purpose bank provided to facilitate the reading of commonly accessed data. this bank contains the program blocking registers and permits direct, multibyte reading of internal registers 08h through 11h . these registers are described in the internal register section. when it is selected, the sequence of bytes read is ssr, followed by internal registers 08h , 09h , 0ah , 0bh , 0ch , 0dh , 0eh , 0fh , 10h , and 11h . bank 2 a special purpose bank provided to facilitate the reading of commonly accessed data. this bank contains the xds program name data from the most recently received current class type 3 packet. bank 3 a special purpose bank provided to facilitate the reading of commonly accessed data. this bank contains the xds network name and call letter data. the ?rst 26 bytes has the xds network name from the most recently received xds channel class type 1 packet. bytes 26 through 31 has the xds call letters data from the most recently received xds channel class type 2 packet n ote : banks 2 and 3 are 33 bytes in length. byte 32 of these banks contains an 8 bit checksum. the checksum is calculated such that the addition of the 32 data bytes and the checksum modulo 256 equals zero. the checksum should always be evaluated after reading this data to ensure that the xds data is not being updated during the read operation. the result is a meaningless combination of two unrelated xds data packets. if a bad checksum is encountered, the read operation should be repeated. i 2 c one-byte write (command) (write= 28h for the 1 st i 2 c address and 2ah for the 2 nd i 2 c address) i 2 c two-byte write (command & data) (write= 28h for the 1 st i 2 c address and 2ah for the 2 nd i 2 c address) start stop slave addr write cmd write data start stop slave addr write cmd i 2 c b us o peration s erial c ommunications i nterface ps000401-tvc0699 z86230preliminary 21 all read sequences output the ssr ?rst. if the serial status register dav bit is set, a 2- or multiple-byte read sequence can be initiated, beginning with a start condition. if the dav bit is not set, the i 2 c master device should not attempt to read any data bytes or the required data can be lost from the z86230 output registers. the i 2 c master device should end the read sequence by failing to acknowledge the received byte. this sequence is repeated until the dav bit becomes true. n ote : in all i 2 c read operations (1-, 2- and 3-byte reads are illustrated in figure 5), the most recent byte read from the z86230 should be acknowledged by the master with a not acknowledge ( nack ). the dav bit of the serial status register ( ssr ) is cleared by the master clocking out the eighth bit of the first data byte read. the dav bit is never cleared by just reading the ssr (one byte read ) alone. all data is output msb first. the masters sequence for reading two data bytes (total of 3 bytes including ssb) from the z86230 is: start slave_address_read/slave_ack ss_byte/master ack first_byte/master ack second_byte/master_nack stop 4.1.5 clock and data transitions the sclk and sda bus lines are normally pulled high with a resistor. data on the sda bus may only change during sclk low time periods. data changes during sclk high periods indicate a start or stop condition as de?ned in table 6. 4.1.6 start condition a high-to-low transition of sda with sclk high is a start condition which must precede any other command. f igure 5. i 2 c b us read (c ommand ) n ote : in all i 2 c read operations, the most recent byte read from the z86230 must be acknowledged by the master with a nack (not acknowledge). start stop slave addr serial status (read= 29h for the 1 st i 2 c address and 2bh for the 2 nd i 2 c address) start stop slave addr serial status (read= 29h for the 1 st i 2 c address and 2bh for the 2 nd i 2 c address) read data1 start stop serial status (read= 29h for the 1 st i 2 c address and 2bh for the 2 nd i 2 c address) read data1 read data2 i 2 c two-byte read (status & data1) i 2 c three-byte read (status, data1, & data2) slave addr i 2 c one-byte read (status only) nack nack nack s erial c ommunications i nterface i 2 c b us o peration 22 z86230preliminary ps000401-tvc0699 4.1.7 stop condition a low-to-high transition of sda with sclk high is a stop condition which ter- minates all communications. 4.1.8 acknowledge all address and data words are serially transmitted to and from the z86230 in eight bit words. a ninth bit time is used for the acknowledge. the acknowledging device pulls the sda bus low during the ninth bit. a not acknowledge ( nack ) is returned by sda = high during the ninth clock time. f igure 6. i 2 c s erial t iming t able 6. i 2 c s erial t iming m in /m ax symbol parameter min max units f sclk clock frequency 100 khz t low clock pulse width low 4.7 C ms t high clock pulse width high 4.0 C ms t r sda and scl rise time C 1.0 ms t f sda and scl fall time C 300 ns t aa clock low to data out valid 0.1 3.5 ms t buf bus free time 4.7 C ms t hd.sta start hold time 4.0 C ms t su.sta start set-up time 4.7 C ms t hd.dat data in hold time 0 C ms t su.dat data in set-up time 250 C ns t su.sto stop set-up time 4.7 C ms t dh data out hold time 100 C ns t i input filter time constant 100 ns sclk t su.sta sda (in) sda (out) t f t hd.sta t aa t high t low t hd.dat t su.dat t dh t r t su.sto t buf s erial p ort c ommands c ommands ps000401-tvc0699 z86230preliminary 23 5. commands 5.1 s erial p ort c ommands the commands must be contained within the startCslave addressCetc. sequence. n ote : in the following command descriptions, the letter h following a command code designates hexadecimal notation. 5.1.1 reset = fbh reset is a 1-byte command. the reset command establishes all of the speci- ?ed default settings in the device, but it does not reset the serial port itself. the reset command must be followed by a no operation ( nop ) command, because reset stays active until deactivated by the nop . this sequence can be entered without the rdy bit being set. 5.1.2 nop = 00h nop is a 1-byte command. the nop command does not affect the status of the rdy bit in the serial status register ( ssr ) and can be executed independent of the rdy status. 5.2 read and write c ommands all register diagrams indicated in this section incorporate the following conven- tions, unless otherwise noted: ? r = read, w = write, x = indeterminate, and res = reserved ? all register bits marked as res must be set to low(0) 5.2.1 read bank select (rbs = fdh ) rds1 is a 2-byte command to select the read data bank. the lower 2 bits of the second data byte select one of four banks of up to 33 bytes. a subsequent i 2 c read deciphers data from the speci?ed bank. 5.2.2 read selects (rds1 = 40h C 51h ) rds1 is a 1-byte command used to initiate a 1-byte read sequence. this activity is performed by moving the contents of the register identi?ed by the address ?eld (ad00:04) of the command to the ?rst location of read bank 0. addresses 00h C 11h are valid in the rds1 command ?eld ad00:04. t able 7. b asic s erial c ommands serial command command code reset fbh nop 00h c ommands w riting to the z86230 24 z86230preliminary ps000401-tvc0699 5.2.3 rds2 = 60hC70h rds2 is a 1-byte command which is used to initiate a 2-byte read sequence by moving the contents of the two consecutive registers, starting with the one identi- ?ed by the address portion of the command (ad00:ad04), to the ?rst 2 locations of read bank 0. only addresses 00hC10h are valid in the rds2 command ?eld ad00:04. n ote : for xds data recovery, when the xds filter register (see control re gisters ) is enabled for the required packets, the z86230 automatically establishes the 2-byte recovery mode and moves the recovered data bytes to the first 2 locations of bank 0. 5.3 w riting to the z86230 5.3.1 wrxx = c0hCd1h the write commands require 2 bytes to execute. the ?rst byte is the write com- mand and includes the z86230 register address (ad00:04) being written. the sec- ond byte is the data to be written. t able 8. rds1Cread o ne b yte (rds1 = 40hC51h ) bit cm7 cm6 cm5 cm4 cm3 cm2 cm1 cm0 0 1 0 ad04 ad03 ad02 ad01 ad00 r/w w w w w w w w w t able 9. rsd2Cr ead t wo b ytes (rds2 = 60hC70h ) bit cm7 cm6 cm5 cm4 cm3 cm2 cm1 cm0 0 1 1 ad04 ad03 ad02 ad01 ad00 r/w w w w w w w w w t able 10. wr xx Cw rite r egister xx (wr x = c0hCd1h ) bit cm7 cm6 cm5 cm4 cm3 cm2 cm1 cm0 1 1 0 ad04 ad3 ad2 ad1 ad0 r/w w w w w w w w w r egisters s ummary c ontrol r egisters ps000401-tvc0699 z86230preliminary 25 6. control registers information controlling the setup and operation of the z86230 are maintained in several registers. the user may read or alter the contents of these registers as required. all register diagrams indicated in this section incorporate the following conven- tions, unless otherwise noted: ? r = read, w = write, x = indeterminate, and res = reserved ? all register bits marked as res must be set to low(0) 6.1 r egisters s ummary 6.1.1 serial status register d 0 Clock. active high, indicating that the internal sync circuits are locked. may be used as an indication of the presence of a video signal. d 1 Cfld. signals the current video ?eld. low = field 2, high = field 1. d 2 Crovr. active high, indicating that the data available in the output buffer is not read out and new data is written over it. d 3 Cintr. active high, indicating that an interrupt other than dav is pending. reserved. d 4 Cwovr. active high, indicating a serial input data overrun. d 5 -res. reserved. d 6 -dav. active high, indicating that data is available to be read out. d 7 Crdy. active high, indicating that the port input buffer is empty. only the nop , reset and read instructions may be sent if rdy is low. 6.1.2 configuration register t able 11. s erial s tatus r egister (a ddress n ot r equired ) bit 7 6 5 4 3 2 1 0 rdy dav res wovr intr rovr fld lock r/w r r r r r r r r t able 12. c onfiguration r egister (a ddress = 00h ) bit 7 6 5 4 3 2 1 0 res res res res res res res tvs r/w r r r r r r/w r r/w c ontrol r egisters r egisters s ummary 26 z86230preliminary ps000401-tvc0699 d 0 Ctvs. selects the television standard. high selects pal and low selects ntsc . the default is ntsc . when pal is selected, the display defaults to 15 tv scan lines per display row. d 1 -res. reserved d 2 -d 7 -res. reserved. 6.1.3 xds data activity register d 0 -res. reserved. d 1 Cxds. indicates xds data is being processed. this bit becomes inactive if no xds data is received within the previous 16 seconds: high = active, low = inac- tive. the reset state is low. d 2 -d 7 -res. reserved. 6.1.4 xds filter register d 0 Ccurr. selects current class packets for output through the serial control port when xds recovery is enabled. d 1 Cfutr. selects future class packets for output through the serial control port when xds recovery is enabled. d 2 Cchan. selects channel information class packets for output through the serial control port when xds recovery is enabled. d 3 Cmisc. selects miscellaneous class packets for output through the serial con- trol port when xds recovery is enabled. d 4 Cpubl. selects public service class packets for output through the serial con- trol port when xds recovery is enabled. d 5 -d 7 Cs 0 Cs 2 . selects a set of secondary parameters, tabulated below, to be used in ?ltering the xds data when xds recovery is enabled. t able 13. xds d ata a ctivity r egister (a ddress = 04h ) bit 7 6 5 4 3 2 1 0 res res res res res res xds res r/w r r r r r r r r t able 14. xds f ilter r egister (a ddress = 05h ) bit 7 6 5 4 3 2 1 0 s 2 s 1 s 0 publ misc chan futr curr r/w r/w r/w r/w r/w r/w r/w r/w r/w r egisters s ummary c ontrol r egisters ps000401-tvc0699 z86230preliminary 27 6.1.5 interrupt request register d 0 -res. reserved. d 1 -dle. active high, indicating that the data line has ended. this bit sets two lines after the data line, and clears about 20 lines before the end of the ?eld. d 2 Ceof. active high, indicating that the video signal is currently at the end of a ?eld. this bit sets during line 262 in field 1 and line 524 in field 2. this bit clears about 2 lines before the end of the ?eld. d 3 Cdlok. active high, indicating that the state of the lock signal has changed. the ssr must be read to determine the current state. d 4 -res. reserved. d 5 Cdxds. active high, indicating that a change in xds activity has occurred. the line 21 activity register must be read to determine if xds data is active. d 6 -d 7 -res. reserved. n ote : except as noted for the case of d1 and d2 above, the master device must write a 1 to the appropriate bit in the interrupt request register to clear the interrupt. writing a 1 to t able 15. xds s econdary f ilter s ettings secondary filter filter value (s0:s2) all 0h time information 1h in band only 2h content advisory 3h vcr information 4h reserved 5h reserved 6h reserved 7h notes: 1. setting this register to 00h turns xds data recovery off. setting bits d 0 through d 4 enables xds data recovery for the classes selected as quali?ed by the secondary filter (bits d 5 Cd 7 ). if bits d 0 Cd 4 are all set to 1, all classes of xds data are output (even reserved and unde?ned). 2. the time information only selection includes the time of day (tod) and local time zone (ltz) packets. 3. vcr information selects tod, ltz, net id, local call letters, impulse capture, tape delay, composite 2, and out-of-band channel number packets for recovery. t able 16. i nterrupt r equest r egister (a ddress = 06h ) bit 7 6 5 4 3 2 1 0 res res dxds res dlok eof dle res r/w r/w r/w r/w r/w r/w r r c ontrol r egisters r egisters s ummary 28 z86230preliminary ps000401-tvc0699 any valid bit position the interrupt request register is equivalent to clearing an inter- rupt request on that bit. 6.1.6 interrupt mask register this register identi?es which activities in the interrupt request register is used to cause an interrupt. setting the bit to 1 enables the interrupt when the correspond- ing event becomes active. setting all bits of this register to zero disables inter- rupts. 6.1.7 content advisory ratings select register 1 this register holds the mpaa content advisory selections made by the viewer. d 0 Cg. the z86230 outputs high on pin 13 when the incoming video program is g-rated according to the mpaa ratings standards, and this bit is set to high. d 1 Cpg. the z86230 outputs high on pin 13 when the incoming video program is pg-rated according to the mpaa ratings standards, and this bit is set to high. d 2 -pg-13. the z86230 outputs high on pin 13 when the incoming video program is pg-13-rated in mpaa ratings standards, and this bit is set to high. d 3 -r. the z86230 outputs high on pin 13 when the incoming video program is r- rated according to the mpaa ratings standards, and this bit is set to high. d 4 -nc-17. the z86230 outputs high on pin 13 when the incoming video program is nc-17-rated according to the mpaa ratings standards, and this bit is set to high. d 5 -x. the z86230 outputs high on pin 13 when the incoming video program is x- rated according to eia-744a and eia-608a speci?cations. mpaa no longer rec- ognizes the x rating. d 6 -not rated. the z86230 outputs high on pin 13 when the incoming video pro- gram is not rated according to the mpaa ratings standards, and this bit is set to high. t able 17. i nterrupt m ask r egister (a ddress = 07h ) bit 76543210 res res dxds res dlok eof dle dav r/w r/w r/w r/w r/w r/w r/w r/w r/w t able 18. c ontent a dvisory r atings s elect r egister 1 (a ddress = 08h ) bit 76543210 res not rated x nc-17 r pg-13 pg g r/w r r/w r/w r/w r/w r/w r/w r/w r egisters s ummary c ontrol r egisters ps000401-tvc0699 z86230preliminary 29 d 7 -res. reserved. this bit must be kept low(0). n ote : the z86230 outputs low when a bit in this register is set to low, and the incoming video program possesses the corresponding mpaa rating. the device outputs high onto pin 13 only when a bit is set to high; it recovers the corresponding mpaa rating in the incoming video program. 6.1.8 content advisory ratings select register 2 this register holds the tv parental guidelines (base content) content advisory selections made by the viewer. d 0 -tv-y. the z86230 outputs high on pin 13 when the incoming video program is tv-y-rated according to the tv parental guidelines ratings standards, and this bit is set to high. d 1 -tv-y7. the z86230 outputs high on pin 13 when the incoming video program is tv-y7-rated according to the tv parental guidelines ratings standards, and this bit is set to high. d 2 -tv-g. the z86230 outputs high on pin 13 when the incoming video program is tv-g-rated according to the tv parental guidelines ratings standards, and this bit is set to high. d 3 -tv-pg. the z86230 outputs high on pin 13 when the incoming video pro- gram is tv-pg-rated according to the tv parental guidelines ratings standards, and this bit is set to high. d 4 -tv-14. the z86230 outputs high on pin 13 when the incoming video program is tv-14-rated according to the tv parental guidelines ratings standards, and this bit is set to high. d 5 -tv-ma. the z86230 outputs high on pin 13 when the incoming video pro- gram is tv-ma-rated according to the tv parental guidelines ratings standards, and this bit is set to high. d 6 -tv-ma. the z86230 outputs high on pin 13 when the incoming video pro- gram is tv-none-rated according to the tv parental guidelines ratings stan- dards, and this bit is set to high. d 7 -res. reserved. this bit must be kept low(0). n ote : the z86230 outputs low when a bit in this register is set to low, and the incoming video program possesses the corresponding tv parental guidelines rating. the device outputs high onto pin 13 only when a bit is set to high; it recovers the corresponding tv t able 19. c ontent a dvisory r atings s elect r egister 2 (a ddress = 09h ) bit 76543210 res none tv-ma tv-14 tv-pg tv-g tv-y7 tv-y r/w r r r/w r/w r/w r/w r/w r/w c ontrol r egisters r egisters s ummary 30 z86230preliminary ps000401-tvc0699 parental guidelines ratings in the incoming video program. this control register is for the base rating of tv parental guidelines. 6.1.9 content advisory ratings select register 3 this register holds the tv parental guidelines (v and s contents) content advi- sory selections made by the viewer. d 0 -tv-pg-s. the z86230 outputs high on pin 13 when the incoming video pro- gram is tv-pg-s-rated according to the tv parental guidelines ratings stan- dards, and this bit is set to high. d 1 -tv-14-s. the z86230 outputs high on pin 13 when the incoming video pro- gram is tv-14-s-rated according to the tv parental guidelines ratings standards, and this bit is set to high. d 2 -tv-ma-s. the z86230 outputs high on pin 13 when the incoming video pro- gram is tv-ma-s-rated according to the tv parental guidelines ratings stan- dards, and this bit is set to high. d 3 -res. reserved. this bit must be kept low(0). d 4 -tv-y7-fv. the z86230 outputs high on pin 13 when incoming video program is tv-y7-fv-rated in tv parental guidelines ratings standards, and this bit is set to high. d 5 -tv-pg-v. the z86230 outputs high on pin 13 when the incoming video pro- gram is tv-pg-v-rated according to the tv parental guidelines ratings stan- dards, and this bit is set to high. d 6 -tv-14-v. the z86230 outputs high on pin 13 when the incoming video pro- gram is tv-14-v-rated according to the tv parental guidelines ratings stan- dards, and this bit is set to high. d 7 -tv-ma-v. the z86230 outputs high on pin 13 when the incoming video pro- gram is tv-ma-v-rated according to the tv parental guidelines ratings stan- dards, and this bit is set to high. n ote : the z86230 outputs low when a bit in this register is set to low and the incoming video program possesses the corresponding tv parental guidelines rating. the device outputs high onto pin 13 only when a bit is set to high; it recovers the corresponding tv parental guidelines rating in the incoming video program. this control register is for the s- and v-rated programs in tv parental guidelines rating. t able 20. c ontent a dvisory r atings s elect r egister 3 (a ddress = 0ah ) bit 76543210 tv- ma-v tv-14- v tv-pg- v tv-y7- fv res tv- ma-s tv-14- s tv-pg- s r/w r/w r/w r/w r/w r/w r/w r/w r/w r egisters s ummary c ontrol r egisters ps000401-tvc0699 z86230preliminary 31 6.1.10 content advisory ratings select register 4 this register holds the tv parental guidelines (l and d content) content advi- sory selections made by the viewer. d 0 -tv-pg-d. the z86230 outputs high on pin 13 when the incoming video pro- gram is tv-pg-d-rated according to the tv parental guidelines ratings stan- dards, and this bit is set to high. d 1 -tv-14-d. the z86230 outputs high on pin 13 when the incoming video pro- gram is tv-14-d-rated according to the tv parental guidelines ratings stan- dards, and this bit is set to high. d 2 -d 3 . reserved. these bits must kept low(0). d 4 -tv-pg-l. the z86230 outputs high on pin 13 when the incoming video pro- gram is tv-pg-l-rated according to the tv parental guidelines ratings stan- dards, and this bit is set to high. d 5 -tv-14-l. the z86230 outputs high on pin 13 when the incoming video pro- gram is tv-14-l-rated according to the tv parental guidelines ratings stan- dards, and this bit is set to high. d 6 -tv-ma-l. the z86230 outputs high on pin 13 when the incoming video pro- gram is tv-ma-l-rated according to the tv parental guidelines ratings stan- dards, and this bit is set to high. d 7 -res. reserved. this bit must be kept low(0). n ote : the z86230 outputs low when a bit in this register is set to low and the incoming video program possesses the corresponding tv parental guidelines rating. the device outputs high onto pin 13 only when a bit is set to high and it recovers the corresponding tv parental guidelines rating in the incoming video program. this control register is for the d- and l-rated programs in tv parental guidelines rating. 6.1.11 content advisory register 1 t able 21. c ontent a dvisory r atings s elect r egister 4 (a ddress = 0bh ) bit 76543210 res tv-ma- l tv-14- l tv-pg- l res res tv-14- d tv-pg- d r/w r r/w r/w r/w r r r/w r/w t able 22. c ontent a dvisory r egister 1 (a ddress = 0ch ) bit 76543210 b 1 da1a0r2r1r0 r/w rrrrrrrr c ontrol r egisters r egisters s ummary 32 z86230preliminary ps000401-tvc0699 d 0 -d 6 . these bits hold the corresponding information recovered from the ?rst byte of the received content advisory ratings packet. d 7 -b. this bit indicates the blocking status. when this bit is high, it indicates that the data from the received content advisory packet matches the user selection contained in one of the content advisory ratings registers, and the pb pin is in the blocking status. 6.1.12 content advisory register 2 d 0 -d 6 . these bits hold the corresponding information recovered from the second byte of the received content advisory ratings packet. d 7 -p. this bit indicates the validity of the data in the recovered content advisory packet. when this bit is high, it indicates that the data from the received content advisory packet is valid. this bit clears if no content advisory packet is received after 5 seconds. 6.1.13 blocking control register 1 d 0 -d 6 -bte. these bits set the block timer which controls the duration of the hold of the blocking signal on a change of channel. the default value of 0 has a hold time of 2 seconds. the time is extended in 2 frames with each binary step. d 7 -blen. these bits enable the blocking capability. blen=0 enables blocking; blen=1 disables blocking. 6.1.14 content advisory ratings select 5 this register holds the canadian english language content advisory selections made by the viewer. t able 23. c ontent a dvisory r egister 2 (a ddress = 0dh ) bit 76543210 p 1 (f)v s l g2 g1 g0 r/w rrrrrrrr t able 24. b locking c ontrol r egister 1 (a ddress = 0eh ) bit 76543210 blen bte r/w r/w r/w r/w r/w r/w r/w r/w r/w t able 25. c ontent a dvisory r atings s elect r egister 5 (a ddress = 0fh ) bit 76543210 res 18+ 14+ pg g c8+ c e r/w r r/w r/w r/w r/w r/w r/w r/w r egisters s ummary c ontrol r egisters ps000401-tvc0699 z86230preliminary 33 d 0 -e. the z86230 outputs high on pin 13 when the incoming video program is e- rated according to the canadian english language ratings standards, and this bit is set to high. d 1 -c. the z86230 outputs high on pin 13 when the incoming video program is c-rated according to the canadian english language ratings standards, and this bit is set to high. d 2 -c8+. the z86230 outputs high on pin 13 when the incoming video program is c8+-rated according to the canadian english language ratings standards, and this bit is set to high. d 3 -g. the z86230 outputs high on pin 13 when the incoming video program is g-rated according to the canadian english language ratings standards, and this bit is set to high. d 4 -pg. the z86230 outputs high on pin 13 when the incoming video program is pg-rated according to the canadian english language ratings standards, and this bit is set to high. d 5 -14+. the z86230 outputs high on pin 13 when the incoming video program is 14+-rated according to the canadian english language ratings standards, and this bit is set to high. d 6 -18+. the z86230 outputs high on pin 13 when the incoming video program is 18+-rated according to the canadian english language ratings standards, and this bit is set to high. d 7 -res. reserved. this bit must be kept low(0). n ote : the z86230 outputs low when a bit in this register is set to low and the incoming video program possesses the corresponding canadian french language rating. the device outputs high onto pin 13 only when a bit is set to high and it recovers the corre- sponding canadian english language rating in the incoming video program. 6.1.15 content advisory ratings select register 6 this register holds the canadian french language content advisory selections made by the viewer. c ontrol r egisters r egisters s ummary 34 z86230preliminary ps000401-tvc0699 d 0 -e. the z86230 outputs high on pin 13 when the incoming video program is e- rated according to the canadian french language ratings standards, and this bit is set to high. d 1 -g. the z86230 outputs high on pin 13 when the incoming video program is g-rated according to the canadian french language ratings standards, and this bit is set to high. d 2 -8ans+. the z86230 outputs high on pin 13 when incoming video program is 8ans+-rated in canadian french language ratings standards, and this bit is set to high. d 3 -13ans+. the z86230 outputs high on pin 13 when incoming video program is 13ans+-rated in canadian french language ratings standards, and this bit is set to high. d 4 -16ans+. the z86230 outputs high on pin 13 when incoming video program is 16ans+-rated in canadian french language ratings standards, and this bit is set to high. d 5 -18ans+. the z86230 outputs high on pin 13 when the incoming video pro- gram is 18ans+-rated according to the canadian french language ratings and this bit is set to high. d 6 -d 7 -res. reserved. these bits must be kept low(0). n ote : the z86230 outputs low when a bit in this register is set to low and the incoming video program possesses the corresponding canadian french language rating. the device outputs high onto pin 13 only when a bit is set to high and it recovers the corre- sponding canadian french language rating in the incoming video program. 6.1.16 blocking control register 2 d 0 -bnr. the z86230 outputs high on pin 13 when the incoming video program has no rating and this bit is set to low. setting this bit to high disables blocking on no rating . t able 26. c ontent a dvisory r atings s elect r egister 6 (a ddress = 10h ) bit 76543210 res res 18ans+ 16ans+ 13ans+ 8ans+ g e r/w r r r/w r/w r/w r/w r/w r/w t able 27. b locking c ontrol r egister 2 (a ddress = 11a h ) bit 76543210 res res res res res res res bnr r/w rrrrrrrr/w xds d ata r ecovery c ontrol r egisters ps000401-tvc0699 z86230preliminary 35 d 1 -d 7 -res. reserved. these bits must be kept low(0). 6.2 xds d ata r ecovery the z86230 is able to recover extended data services (xds) information from the input video signal. this data, formatted according to eia-608a, can contain a wide variety of information about current and future programs, the channel cur- rently tuned, other channels, and miscellaneous data, including time of day. xds data packets are tagged according to a class/type system de?ned by eia- 608a. the z86230 can be programmed to ?lter the xds data stream to extract only the classes of interest to the application. an additional level of ?ltering is provided that permits selection of certain groups of packets that are of use in spe- ci?c applications. xds ?ltering reduces the traf?c on the serial bus, reduces the load of the tv/vcr control processor, and simpli?es external xds decoding. xds data recovery is enabled by selecting one or more classes in the xds filter register. optionally, a secondary ?lter code can be speci?ed which further limits the packets to be recovered. when xds recovery is enabled, ?ltered data pairs are loaded into the ?rst two data locations of bank 0 immediately upon receipt. the dav bit of the serial status register ( ssr ) then goes high, indicating the avail- ability of two output bytes. when the xds filter register is set to 00h (the default state), xds recovery is disabled. c aution : when xds data recovery is enabled, the external controller should never per- form any other read operation, except ssr reads, in the beginning of field 2. commands other than read selects do not interfere with xds data recovery regardless of their position in the video frame. some examples of z86230 write commands that could be used to set the xds filter register are indicated in table 28. the xds filter register bit assignments are de?ned in table 30. c ontrol r egisters xds d ata r ecovery 36 z86230preliminary ps000401-tvc0699 6.2.1 filtered xds data format filtered xds data is output from the z86230 in the order it is received on line 21. in other words, think of the z86230 xds ?lter function as creating a new, smaller stream of xds data packets. this new data stream looks exactly as though the class and type speci?ed in the xds filter register ( 05h ) are the only data encoded on line 21 of field 2. the ?ltered data output from the z86230 is in full compliance with eia-608 speci?cations for xds data streams (headers and con- trol codes intact). refer to the n ote paragraph on the next page for a special exception to this rule. xds data and header information (including start , continue , and end com- mands) are passed through the ?lter for the xds class and type speci?ed in the xds filter register. all other line 21 data is ?ltered out. this data does not out- put or generate a data available ?ag ( dav ) in the serial status register ( ssr ). to properly read ?ltered xds data from the z86230, the master device must ?rst write the xds filter register ( 05h ) with its required xds class and type infor- mation. for example, in the z86230, in order to extract only the line 21 pro- gram rating information, the master must write the value 61h to the xds filter register. the master should then poll the state of the dav bit in the ssr until dav = 1 . as soon as dav = 1 , the master may initiate a 3-byte read in rbs read bank 0 mode (xds data bytes always arrive in pairs, so it is safe to read the ?rst 2 bytes of read bank 0 when dav = 1 in the ssb). a 3-byte read always yields two data bytes, which in this case are the ?rst 2 bytes of the current class, program rating type xds data stream encountered on line21, field 2. the master device must then interpret those 2 bytes according to eia-608 speci?cations for current class, program rating type data. refer to eia-608 for the appropriate data formats. t able 28. xds d ata e xtraction e xample f ilter s ettings {write command, filter code} xds filter output {c5,41} all in band; current class packets recovered. {c5,61} program rating; current class packets recovered. this ?lter may be used for program blocking data packet recovery. {c5,1f} all xds packets recovered. {c5,01} all current class packets recovered. {c5,28} time information recovered. this ?lter extracts the time of day (tod) and local time zone (ltz) packets from the miscellaneous class data. this ?lter may be used to implement auto clock- setting in tvs, and vcrs. {c5,9f} vcr information recovered. this ?lter selects tod, ltz, net id, local call letters, impulse capture, tape delay, composite 2, and out-of-band channel number packets for recovery. xds d ata r ecovery c ontrol r egisters ps000401-tvc0699 z86230preliminary 37 the xds ?lters on the z86230 greatly reduce the amount of field 2 data passed on to the master device for further processing and interpretation; however, the master device must still interpret the ?ltered data stream in accordance with eia- 608a. in other words, only the selected xds data class and type packets are cho- sen. the ?ltered data stream contains all of the xds command and data packets. though the z86230 ?ltered data stream is in full compliance with the eia-608 speci?cation, the master device must still interpret the necessary packets to ensure full compliance with eia-608a. n ote : the z86230 xds filter for program rating information functions differently than all other z86230 predefined xds filters. this change has been made to minimize the amount of data passed through the program rating xds filter, thereby minimizing the interpretation and communications load on the master device. when the xds filter regis- ter is set to 61h (class= 01h (current), type= 05h (program rating) the only data from line 21 field 2 that passes through the filter is: 1. program rating packet: [ xxh,xxh ]. the current class program rating data byte pair as defined in eia-608. the programs rating is encoded per eia-608 in the xxh byte pair. 2. the end packet [ 0fh , chksum ]. a 2-byte packet that includes a chksum computed per eia-608a. the checksum calculation includes the start packet [ 01h,05h ] even though this value was not passed through the filter. c ontrol r egisters z86230 c ommands and r egisters s ummary 38 z86230preliminary ps000401-tvc0699 6.3 z86230 c ommands and r egisters s ummary t able 29. z86230 s ummary of c ontrol c ommands name code function reset fbh reset is 1-byte command sequence serial communication. the reset command establishes all of the speci?ed default settings in the device; however, it does not reset the serial port itself. this sequence can be entered without rdy being set. nop 00h nop is a 1-byte command for use in serial communication. the nop command does not affect the status of the rdy bit in the serial status register (ssr) and can be executed independent of the rdy status. rds1 40h C 51h rds1 is a 1-byte command used to initiate a 1- byte read sequence by moving the contents of the register identi?ed by the address ?eld (ad00:04) of the command to the output register. addresses 00h C 11h are valid in the rds1 command ?eld ad00:04. rds2 60h C 70h rds2 is a 1-byte command which is used to initiate a 2-byte read sequence. this activity is accomplished by moving the contents of the two consecutive registers, starting with the one identi?ed by the address portion of the command (ad00:ad04), to the output registers. only addresses 00h C 10h are valid in the rds2 command ?eld ad00:04. wrxx c0h C d1h , xxh the write commands require 2 bytes to execute. the ?rst byte is the write command includes the z86230 register address (ad00:04) being written. the second byte ( xxh ) is the data to be written. rbs fdh , 0xh rbs is 2-byte command to select the read data bank. the 2 lsbs of the second byte ( 0xh ) select one of four banks of up to 33 bytes. subsequent i 2 c reads interpret data from this bank. p rogram b locking m ap c ontrol r egisters ps000401-tvc0699 z86230preliminary 39 6.4 p rogram b locking m ap the following matrices demonstrate the program-blocking response of the z86230. the ?rst column lists the possible entries into the content advisory rat- ing registers. the ?rst row lists the ratings that might be recovered from the received content advisory packet. blocking action is indicated by the black boxes. each matrix shows the response to the possible user selections entered into the content advisory rating registers when programs having speci?c content advi- sory packets are received. for example, as shown in the tv parental guidelines rating matrix, entering the viewer selection from tv-pg d in register 09b causes blocking whenever the received content advisory packet is tv-pg d, tv-pg vd, tv-pg sd, tv-pg ld, tv-pg vsd, tv-pg vld, tv-pg sld or tv-pg vsld . t able 30. s ummary of z86230 i nternal r egisters register name addr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 serial status register (ssr) none rdy dav res wovr intr rovr fld lock con?guration 00h res res res res res res res tvs xds data activity 04h res res res res res res xds res xds filter 05h s 2 s 1 s 0 publ misc chan futr curr interrupt request register 06h res res dxds res dlok eof dle res interrupt mask register 07h res res dxds res dlok eof dle dav content advisory rating select 1 08h res not rated x nc-17 r pg-13 pg g content advisory rating select 2 09h res none tv-ma tv-14 tv-pg tv-g tv-y7 tv-y content advisory rating select 3 0ah tv-ma v tv-14 v tv-pg v tv-y7 fv res tv-ma s tv-14 s tv-pg s content advisory rating select 4 0bh res tv-ma l tv-14 l tv-pg l res res tv-14 d tv-pg d content advisory1 0ch b 1 da1a0r2r1r0 content advisory 2 0dh p 1 (f)v s l g2 g1 g0 blocking control 1 0eh blen bte content advisory rating select 5 0fh res 18+ 14+ pg g c8+ c e content advisory rating select 6 10h res res 18ans+ 16ans+ 13ans+ 8ans+ g e blocking control 2 11h res res res res res res res bnr n ote : all register bits marked as res must be set to low(0). c ontrol r egisters p rogram b locking m ap 40 z86230preliminary ps000401-tvc0699 table 31. mpaa matrix (use content advisory rating register 08h ) g pg pg-13 r nc-17 x nr g pg pg-13 r nc-17 x nr t able 32. tv p arental g uidelines m atrix (u se c ontent a dvisory r ating r egister 09h , 0ah , 0bh ) y y7 g pg 14 ma CCf v CCvsldv s v l v d s l s d l d v s l v s d v l d s l d v s l d Cvsldv s v l v d s l s d l d v s l v s d v l d s l d v s l d Cvslv s v l s l v s l y y7 y7-fv g pg pg-v pg-s pg-l pg-d 14 14-v 14-s 14-l 14-d ma ma-v ma-s ma-l n ote : C denotes a base rating. p rogram b locking m ap c ontrol r egisters ps000401-tvc0699 z86230preliminary 41 t able 33. c anadian e nglish m atrix (u se c ontent a dvisory r ating r egister 0fh ) e c c8+ g pg 14+ 18+ e c c8+ g pg 14+ 18+ t able 34. c anadian f rench m atrix (u se c ontent a dvisory r ating r egister 10h ) e g 8ans+ 13ans+ 16ans+ 18ans+ e g 8ans+ 13ans+ 16ans+ 18ans+ d emonstration p rograms c ommunicating with the z86230 42 z86230preliminary ps000401-tvc0699 7. demonstration programs 7.1 c ommunicating with the z86230 communications with the z86230 is accomplished using its serial communica- tions interface (it is assumed that the user is familiar with the serial protocol requirements). n ote : in the following descriptions, g eneral c ommands d emonstration p rograms ps000401-tvc0699 z86230preliminary 43 7.4 g eneral c ommands 7.5 scripti p rogram this program is designed to send any number of 1 or 2-byte commands to the z86230. the list of commands to be executed are contained in script ?les that have the extension .ser . for example, a ?le called filfa.ser contains the 1-byte command: {c5, 02} * set xds ?lter to all future class the program is invoked by typing: si file_name d emonstration p rograms s cript f iles 44 z86230preliminary ps000401-tvc0699 7.6.1 configuration register script files 7.6.2 xdscap program this program performs the task of xds data recovery. xds recovery must ?rst be enabled through the appropriate xds filter command. script ?le examples for setting the xds filter are shown below. the program is invoked by typing: si file_name s cript f iles d emonstration p rograms ps000401-tvc0699 z86230preliminary 45 7.6.3 xds filter register script files file name command function fila {c5,1f} set xds ?lter to all fil0 {c5,00} set xds ?lter to none; turns off xds recovery filca {c5,01} set xds ?lter to all current class filc {c5,41} set xds ?lter to current, in band class filfa {c5,02} set xds ?lter to all future class filch {c5,04} set xds ?lter to channel class film {c5,08} set xds ?lter for misc. info filtime {c5,28} set xds ?lter time only filvcr {c5,9e} set xds ?lter vcr info e lectrical c haracteristics a bsolute m aximum r atings 1 46 z86230preliminary ps000401-tvc0699 8. electrical characteristics 8.1 a bsolute m aximum r atings 1 8.2 s tandard t est c onditions the characteristics listed below apply for standard test conditions as noted. all voltages are referenced to ground. positive current ?ows into the referenced pin (figure 7). symbol parameter value unit v dd dc supply voltage C0.5 to 6.0 v v in dc input voltage C0.5 to v dd +0.5 v v out dc output voltage C0.5 to v dd +0.5 v i in c aution : dc input current per pin +10 ma i out dc output current per pin +20 ma i dd dc supply current +30 ma p d power dissipation per device 300 mw t stg storage temperature C65 to +150 oc t l lead temperature, 1 mm from case for 10 seconds 260 oc notes: 1. voltages referenced to v ss (a). maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the limits speci?ed in the dc and ac characteristics tables or pin description section. f igure 7. s tandard t est l oad from output under test 150 pf 250 m a 2.1 k w +5v dc c haracteristics e lectrical c haracteristics ps000401-tvc0699 z86230preliminary 47 8.3 dc c haracteristics 8.4 ac and t iming c haracteristics 8.4.1 composite video input 8.5 e lectrical c haracteristics 8.5.1 non-standard video signals non-standard video signals must have the following characteristics: t able 36. dc c haracteristics t a = 0oc to +70oc; v dd = +4.75v to +5.25v symbol parameter conditions min. max. unit v il input voltage low 0 0.2 v dd v v ih input voltage high 0.7 v dd v dd v v ol output voltage low i ol = 1.00 ma C 0.4 v v oh output voltage high i oh = 0.75 ma v dd C0.4v C2 v i il input leakage 0v, v dd C3.0 3.0 ma i dd supply current 30 ma kf vco gain C tbd mhz/v i lp loop filter current C tbd ma t able 37. c omposite v ideo i nput parameter conditions amplitude 1.0v p-p 3 db polarity sync tips negative bandwidth 600 khz signal type interlaced max input r 470 ohms dc offset signal must be ac-coupled with a minimum series capacitance of 0.1 f t able 38. n on -s tandard v ideo s ignals parameter conditions sync amplitude 200 mv minimum vertical pulse width 3h 0.5h vertical pulse tilt 20 mv maximum e lectrical c haracteristics e lectrical c haracteristics 48 z86230preliminary ps000401-tvc0699 8.5.2 hin/xin signal input h timing phase step (head switch) 10 s maximum fh deviation (long term) 0.5% maximum fh p-p deviation (short term) 0.3% maximum vertical sync signal the internal sync circuits lock to all 525- or 625-line signals that exhibit a vertical sync pulse that meets the following conditions: 1. it is at least 3h 0.5h wide. 2. it starts at the proper 2h boundary for its field. 3. if equalizing pulse serrations are present, they must be less than 0.125h in width. minimum signal- to-noise the z86230 functions down to a 25 db signal-to-noise ratio (ccir-weighted) with one error per row or better at that level. ratio to composite video input table 39. hin/xin signal input mode parameter conditions 1. hin input (video lock mode) amplitude cmos level signal where low 0.2 v cc polarity any frequency 15,734.263 hz @ 3% (hin lock mode) amplitude cmos level signal where low 0.2 v cc polarity any frequency same as display horizontal flyback (hfb) pulse 2. xin input (xtal) frequency 32.768 khz frequency tolerance 20ppm @ t a = 25c, cl = 12.5pf (clock) amplitude cmos level signal where low 0.2 v cc frequency 32.768 khz 2% t able 38. n on -s tandard v ideo s ignals parameter conditions e lectrical c haracteristics e lectrical c haracteristics ps000401-tvc0699 z86230preliminary 49 8.5.3 line 21 input parameters (at 1.0v p-p) line 21 must be in its proper position to the leading edge of the vertical sync sig- nal. t able 40. l ine 21 i nput p arameters parameter conditions code amplitude 50 ire* code zero level 5 ire, +15 ire relative to back porch start of code 10.5 0.5 s (measure from the midpoint of the leading edge of the composite video hsync pulse to the midpoint of the rising edge of the ?rst clock run-in cycle.) start of the data 3.972 ms, C0.00 s, +0.30 s (measure from the midpoint of the falling edge of the most recent clock run-in cycle to the midpoint of the rising edge of the start bit.) n ote : *a relative unit of measure developed by the institute of radio engineers (ire). one ire equals 1/140th of the composite video signal's peak-to-peak voltage. ire is the former name of what is now known as the institute of electrical and electronics engineers (ieee). a pplication i nformation r eference d esigns 50 z86230preliminary ps000401-tvc0699 9. application information the recommended schematic, component placement, and pcb layout for a single- sided dip design are provided in the following ?gures. i 2 c communication and xtal mode are chosen in the reference circuit design. emi and noise in the video frequency range is kept to an absolute minimum by running the ground plane underneath the entire z86230 package length. this design is recommended for both soic and dip package styles. 9.1 r eference d esigns f igure 8. z86230 r eference c ircuit . sda sclk nrst i 2 c sel lpf csync video 13 14 15 4 1 pb x out x in v dd rref v ss v ss (a) c6 c5 c7 r5 c3 r4 c4 r1 ca1 cb1 l1 +5v 3 5 7 8 9 12 10 6 11 i 2 c bus y1 r2 r3 c1 c2 h sel +5v 2 z86230 intro 17 r eference d esigns a pplication i nformation ps000401-tvc0699 z86230preliminary 51 t able 41. r ecommended c omponent v alues for z86230 r eference c ircuit component value units r1 10 k w r2 22 m w r3 470 k w r4 470 w r5 6.8 k w c1 10 pf c2 20 pf c3 0.1 f c4 560 pf c5 0.1 f c6 6800 pf c7 0.068 f ca1 0.1 f cb1 0.1 f l1 bead n/a y1 32.768 khz u1 z86230 n/a a pplication i nformation r eference d esigns 52 z86230preliminary ps000401-tvc0699 f igure 9. pcb d esign of z86230 r eference c ircuit vdd(+5v) vss sclk sda nrst video c2 c1 y1 c4 c5 c6 r5 c7 r4 c3 r1 ca1 cb1 l1 r3 r2 u1 intr o i 2 c sel r eference d esigns p ackaging ps000401-tvc0699 z86230preliminary 53 10. packaging f igure 10. 18-l ead dip p ackage d iagram f igure 11. 18-l ead soic p ackage d iagram o rdering i nformation p art n umber d escription 54 z86230preliminary ps000401-tvc0699 11. ordering information for fast results, contact your local zilog sale of?ces for assistance in ordering the part(s) required. 11.1 p art n umber d escription the zilog part numbers consist of a number of components. e xample : part number z86230 12 p s c is a z86230, 12-mhz dip, 0oc to +70oc, plastic standard flow, and consists of the codes indicated in the following table. z86230 (12 mhz) standard temperature 18-pin dip 18-pin soic z8623012psc z8623012ssc z zilog pre?x 86230 product number 12 speed (in mhz) p package s temperature c environmental flow p art n umber d escription p recharacterization p roduct ps000401-tvc0699 z86230preliminary 55 12. precharacterization product the product represented by this document is newly introduced and zilog has not completed the full characterization of the product. the document states what zilog knows about this product at this time, but additional features or non-con- formance with some aspects of the document may be found, either by zilog or its customers in the course of further application and characterization work. in addition, zilog cautions that delivery may be uncertain at times, due to start-up yield issues. zilog, inc. 910 east hamilton avenue, suite 110 campbell, ca 95008 telephone (408) 558-8500 fax 408 558-8300 internet: http://www .zilog.com c ustomer f eedback f orm p art n umber d escription 56 z86230preliminary ps000401-tvc0699 customer feedback form z86230 p roduct s pecification if you experience any problems while operating this product, or if you note any inaccuracies while reading this product speci?cation, please copy and complete this form, then mail or fax it to zilog (see return information, below). we also welcome your suggestions! c ustomer i nformation p roduct i nformation r eturn i nformation zilog system test/customer support 910 e. hamilton avenue, suite 110, ms 4C3 campbell, ca 95008 fax: (408) 558-8536 email: tools@zilog.com p roblem d escription or s uggestion provide a complete description of the problem or your suggestion. if you are reporting a speci?c problem, include all steps leading up to the occurrence of the problem. attach additional pages as necessary. ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ name country company phone address fax city/state/zip e-mail serial # or board fab #/rev. # software version document number host computer description/type ps000401-tvc0699 z86230?preliminary 57 i ndex n umerics 14+-rated . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 18+-rated . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 18-lead dip package . . . . . . . . . . . . . . . . . 53 18-lead soic package . . . . . . . . . . . . . . . . 53 2-wire bus . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3-byte read . . . . . . . . . . . . . . . . . . . . . . . . 36 a absolute maximum ratings . . . . . . . . . . . . 46 ac and timing characteristics . . . . . . . . . . 47 acknowledge . . . . . . . . . . . . . . . 11, 18 - 19 , 22 application information . . . . . . . . . . . . . . . 50 architectural overview . . . . . . . . . . . . . . . . . 9 ascii characters . . . . . . . . . . . . . . . . . . . . . 44 auto clock set . . . . . . . . . . . . . . . . . . . . . . . 9 b base rating . . . . . . . . . . . . . . . . . . . . . . . 30 , 40 basic serial commands . . . . . . . . . . . . . . . 23 block diagram and operational overview . . 9 block timer . . . . . . . . . . . . . . . . . . . . . . . . 32 blocking 32, 39 blocking control registers . . . . . . . . . . 32, 34 blocking no rating programs . . . . . . . . . . 17 bus conditions . . . . . . . . . . . . . . . . . . . . . . 18 bus protocol . . . . . . . . . . . . . . . . . . . . . . . . 18 busy bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 byte pairs . . . . . . . . . . . . . . . . . . . . . . . . . . 44 c c8+-rated . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 call letter . . . . . . . . . . . . . . . . . . . . 20 , 27 , 36 canadian english language content advisory . . . . . . . . . . . . . . . . . . . 32 canadian french language content advisory . . . . . . . . . . . . . . . . . . . 33 chan . . . . . . . . . . . . . . . . . . . . . . . . . . 26 , 39 channel information class packets . . . . . . . 26 chksum . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 class type 2 packet . . . . . . . . . . . . . . . . . . . . 20 class type 3 packet . . . . . . . . . . . . . . . . . . . . 20 class/type system . . . . . . . . . . . . . . . . . . . . 35 clock and data transitions . . . . . . . . . . . . . 21 command processor . . . . . . . . . . . . . . . . . . 10 commands . . . . . . . . . . . . . . . . . . . . . . . . . 23 communicating with the z86230 . . . . . . . . 42 comp sync . . . . . . . . . . . . . . . . . . . . . . . . . 10 composite video . . . . . . . . . . . . . . . 9 , 14, 49 input . . . . . . . . . . . . . . . . . . . . . . . 9, 10, 47 signal . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 configuration register . . . . . . . . . . . . . . . . 25 script files . . . . . . . . . . . . . . . . . . . . . . . 44 content advisory packet . . . . . . . . . . . . . . . . . . . 9 , 15 , 32 , 39 rating registers . . . . . . . . . . . . . . . . . . . . 39 rating select register . . . . . . .15, 28-31, 33 registers . . . . . . . . . . . . . . . . . . . . . . .31-32 continue . . . . . . . . . . . . . . . . . . . . . . . . . 36 control+c (^c) . . . . . . . . . . . . . . . . . . . 42 , 44 counting circuits . . . . . . . . . . . . . . . . . . . . 10 c-rated . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 csync . . . . . . . . . . . . . . . . . . . . . . . . . 10 , 14 curr . . . . . . . . . . . . . . . . . . . . . . . . . . 26 , 39 current class . . . . . . . . . . . . . . . . . . . . . . . 36 packets . . . . . . . . . . . . . . . . . . . . . . . 26 , 36 program rating data . . . . . . . . . . . . . . . . 37 customer feedback form . . . . . . . . . . . . . . 56 customer information . . . . . . . . . . . . . . . . . 56 d d- and l-rated programs . . . . . . . . . . . . . . 31 data available flag . . . . . . . . . . . . . . . . . . . . 36 data clock . . . . . . . . . . . . . . . . . . . . . . . . . . 10 recovery circuits . . . . . . . . . . . . . . . . . . . 10 data slicer . . . . . . . . . . . . . . . . . . . . . . . . . 10 data available flag ( dav ) . . . . . . . . . . 25 , 39 dav bit . . . . . . . . . . . . . . . . . . .20 - 21 , 35 - 36 dc characteristics . . . . . . . . . . . . . . . . . . . 47 dclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 phase lock . . . . . . . . . . . . . . . . . . . . . . . . 10 decoder control circuit block . . . . . . . . . . 10 demonstration programs . . . . . . . . . . . . . . 42 dip . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 , 54 dip package . . . . . . . . . . . . . . . . . . . . . . . . 50 disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 dle . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 - 28 dlok . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 - 28 dxds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 58 z86230?preliminary ps000401-tvc0699 e eiaC608 . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 eiaC608a . . . . . . . . . . . . . . . . . . . . . 9 , 35 , 37 eia-744a . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 electrical characteristics . . . . . . . . . . . . 46 - 47 electronics industry association . . . . . . . . . 9 emi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 end packet . . . . . . . . . . . . . . . . . . . . . . . . . 37 eof . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 - 28 e-rated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 extended data services . . . . . . . . . . . . . 9 , 35 f field 1 . . . . . . . . . . . . . . . . . . . . . . . 25 , 27, 42 field 2 . . . . . . . . . . . . . . . 9 , 25 , 27 , 35 , 36 - 37 field counter ( fld cntr ) . . . . . . . . . . . . . . 10 fld . . . . . . . . . . . . . . . . . . . . . . . . . 25 , 39 , 42 fully programmable . . . . . . . . . . . . . . . . . 9 , 17 futr . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 , 39 future class packets . . . . . . . . . . . . . . . . . . 26 g general commands . . . . . . . . . . . . . . . . . . . 43 g-rated . . . . . . . . . . . . . . . . . . . . . . 28 , 33 - 34 h h lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 h sel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 h signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 hex values . . . . . . . . . . . . . . . . . . . . . . . . . . 44 hin input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 lock mode . . . . . . . . . . . . . . . . . . . . . . . 48 mode . . . . . . . . . . . . . . . . . . . . . . . . . 13 - 14 hin/xin . . . . . . . . . . . . . . . . . . . . . . . 9 , 13 - 14 input signal . . . . . . . . . . . . . . . . . . . . . . . 10 signal input . . . . . . . . . . . . . . . . . . . . . . . 48 horizontal (h) lock circuit . . . . . . . . . . . . . 10 horizontal frequency signal . . . . . . . . . . . . . 14 horizontal timing signal . . . . . . . . . . . . . 9 - 10 i i 2 c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 interface . . . . . . . . . . . . . . . . . . . . . . . . . 19 operation . . . . . . . . . . . . . . . . . . . . . . . . 18 i 2 c communication . . . . . . . . . . . . . . . . . . . 50 i 2 c master . . . . . . . . . . . . . . . . . . . . . . . 15 , 21 i 2 c operation . . . . . . . . . . . . . . . . . . . . . . . 42 i 2 c sel . . . . . . . . . . . . . . . . . . . . . . 13 , 16 , 18 i 2 c serial communication port . . . . . . . . . . . . . . 9 , 17 control interface . . . . . . . . . . . . . . . . . . . 16 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 i 2 c slave device . . . . . . . . . . . . . . . . . . . . . 42 i 2 c start condition . . . . . . . . . . . . . . . . . 19 i 2 c stop condition . . . . . . . . . . . . . . . . . . 19 iico program . . . . . . . . . . . . . . . . . . . . . . . 42 impulse capture . . . . . . . . . . . . . . . . . . 27 , 36 indirect addressing . . . . . . . . . . . . . . . . . . . 11 input signals . . . . . . . . . . . . . . . . . . . . . . . . . 9 internal registers . . . . . . . . . . . . . . . . . 20, 39 interrupt mask register . . . . . . . . . . . . . . . . . . 15 , 28 output . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 request register . . . . . . . . . . . . . . . . . . . 27 intr . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 , 39 intro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 l least significant bit ( lsb ) . . . . . . . . . . . . . 18 line 21 . . . . . . . . . . . . . . . . . . . . . . . . . . 9 , 16 activity register . . . . . . . . . . . . . . . . . . . 27 field 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 input parameters . . . . . . . . . . . . . . . . . . . 49 program rating information . . . . . . . . . . 36 line counter ( line cntr ) . . . . . . . . . . . . . . 10 local time zone . . . . . . . . . . . . . . . . . . 27 , 36 lock . . . . . . . . . . . . . . . . . . . . . 25 , 27 , 39 , 42 loop filter ( lpf ) . . . . . . . . . . . . . . . . . . 15 , 47 ltz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 , 36 m master device . . . . . . . . . . . 18 - 19 , 21 , 27 , 36 misc . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 , 39 miscellaneous class data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 packets . . . . . . . . . . . . . . . . . . . . . . . . . . 26 mpaa content advisory . . . . . . . . . . . . . . . . . . 28 rating . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 ratings standards . . . . . . . . . . . . . . . . . . 28 n no connect (nc) . . . . . . . . . . . . . . . . . . . . . 15 ps000401-tvc0699 z86230?preliminary 59 nc-17-rated . . . . . . . . . . . . . . . . . . . . . . . . . 28 net id . . . . . . . . . . . . . . . . . . . . . . . . . . 27 , 36 no operation (nop) . . . . . . . . . . . . . . . . . . . 23 non-standard video signals . . . . . . . . . . . . 47 nop command . . . . . . . . . . . . . . . . . . . 23 , 42 not acknowledge (nack) . . . . . . . 19 , 21 - 22 not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 not rated . . . . . . . . . . . . . . . . . . . . . . . 28 , 39 nrst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 ntsc . . . . . . . . . . . . . . . . . . . 9 , 14 , 16 - 17 , 26 ntsc line 21 . . . . . . . . . . . . . . . . . . 9 , 16 , 26 o ordering information . . . . . . . . . . . . . . . . . 54 out-of-band channel number packets .27 , 36 p packaging . . . . . . . . . . . . . . . . . . . . . . . . . . 53 pal . . . . . . . . . . . . . . . . . . . . 9 , 16 - 17 , 26 , 44 part number description . . . . . . . . . . . . . . . 54 pb . . . . . . . . . . . . . . . . . . . . . . . . 9 , 15 - 16, 32 pg-13-rated . . . . . . . . . . . . . . . . . . . . . . . . . 28 pg-rated . . . . . . . . . . . . . . . . . . . . . . . . 28 , 33 picture-in-picture (pip) . . . . . . . . . . . . . . . . . 9 pin descriptions . . . . . . . . . . . . . . . . . . . . . 13 power supply . . . . . . . . . . . . . . . . . . . . . . . 15 precharacterization . . . . . . . . . . . . . . . . . . . 55 problem description . . . . . . . . . . . . . . . . . . 56 product information . . . . . . . . . . . . . . . . . . 56 program blocking . . . . . . . . . . . . . . . . . 15 - 17 data packet recovery . . . . . . . . . . . . . . . 36 map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 registers . . . . . . . . . . . . . . . . . . . . . . . . . . 20 signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 program rating information . . . . . . . . . 36 - 37 program rating xds filter . . . . . . . . . . . . . 37 program unblock hold off . . . . . . . . . . . . . 17 program-blocking response . . . . . . . . . . . . . 39 publ . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 , 39 public service class . . . . . . . . . . . . . . . . . . 26 r rbs . . . . . . . . . . . . . . . . . . . . . .20 , 23 , 36 , 38 rds1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 , 38 rds2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 , 38 rdy . . . . . . . . . . . . . . . . . .20 , 23 , 25 , 38 , 39 bit . . . . . . . . . . . . . . . . . . 19 , 23 , 38 , 42 - 43 status . . . . . . . . . . . . . . . . . . . . . . 23 , 38 , 43 read . . . . . . . . . . . . . . . . . 11 , 13 , 18 - 19 , 25 and write commands . . . . . . . . . . . . . 23 bank 0 mode . . . . . . . . . . . . . . . . . . . . . . 36 bank select . . . . . . . . . . . . . . . . . . . . 20 , 23 select . . . . . . . . . . . . . . . . . . . 20 , 23 , 35 sequence . . . . . . . . . . .11 , 20 - 21 , 23 - 24 , 38 reading data using the i 2 c bus . . . . . . . . 20 reference designs . . . . . . . . . . . . . . . . . . . 50 registers summary . . . . . . . . . . . . . . . . . . . 25 reset . . . . . . . . . . . 13 , 17 , 23 , 25 , 38 , 42 - 43 reset state . . . . . . . . . . . . . . . . . . . . . . . . 26 resistor reference . . . . . . . . . . . . . . . . . . . 15 return information . . . . . . . . . . . . . . . . . . . 56 rovr . . . . . . . . . . . . . . . . . . . . . . . . . . 25 , 39 r-rated . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 rref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 s s- and v-rated programs . . . . . . . . . . . . . . . 30 sclk . . . . . . . . . . . . . . . 15 - 16 , 18-19 , 21 - 22 script files . . . . . . . . . . . . . . . . . . . . . . .43 - 45 scripti . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 sda . . . . . . . . . . . . . . . . . . . . . . 15 , 19 , 21 - 22 sda line . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 serial clock . . . . . . . . . . . . . . . . . . . . . . 15, 18 serial communications interface . . . . . 18, 42 serial control port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 process . . . . . . . . . . . . . . . . . . . . . . . . . . 42 serial data . . . . . . . . . . . . . . . . . . . . . . . . . 15 serial port . . . . . . . . . . . . . . . . . 16 , 23 , 38 , 42 serial status register ( ssr ) . . . . 19, 21, 23 , 25, 27, 35, 38 , 42-43 dav bit . . . . . . . . . . . . . . . . . . . . . . . . . 21 single-sided dip design . . . . . . . . . . . . . . . 50 slave address . . . . . . . . . . 9 , 11 , 13 , 16 , 18 , 44 read . . . . . . . . . . . . . . . . . . . . . . . . .18 - 19 write . . . . . . . . . . . . . . . . . . . . . . . .18 - 19 slave device . . . . . . . . . . . . . . . . . . . . . . . . . 18 slice level . . . . . . . . . . . . . . . . . . . . . . . . . . 10 soic . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 , 54 soic package . . . . . . . . . . . . . . . . . . . . . . . 50 ssb . . . . . . . . . . . . . . . . . . . . . . . . . 21 , 36 , 43 standard test conditions . . . . . . . . . . . . . . 46 start . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 condition . . . . . . . . . . . . . . . . . . . 18 - 19 , 21 packet . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 60 z86230?preliminary ps000401-tvc0699 status register data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 rdy bit . . . . . . . . . . . . . . . . . . . . . . . . . . 20 stop condition . . . . . . . . . . . . . . . . 18 , 21-22 sync slice level . . . . . . . . . . . . . . . . . . . . . . 14 sync slicer . . . . . . . . . . . . . . . . . . . . . . . . . 10 t tape delay . . . . . . . . . . . . . . . . . . . . . . 27 , 36 television decoder circuits act of 1990 . . . 9 television vbi . . . . . . . . . . . . . . . . . . . . . . . . 9 the i 2 c bus protocol . . . . . . . . . . . . . . . . . 18 time of day (tod) . . . . . . . . . . . . . . . . 27 , 36 timing and counting circuits . . . . . . . . . . . 10 timing characteristics . . . . . . . . . . . . . . . . 47 tv parental guidelines . . . . . . . . . . . . . . . . 29 rating matrix . . . . . . . . . . . . . . . . . . . . . 39 ratings standards . . . . . . . . . . . . . . . 29 - 30 tv-14-l-rated . . . . . . . . . . . . . . . . . . . . . . . 31 tv-14-rated . . . . . . . . . . . . . . . . . . . . . . . . . 29 tv-14-s-rated . . . . . . . . . . . . . . . . . . . . . . . 30 tv-14-v-rated . . . . . . . . . . . . . . . . . . . . . . 30 tv-g-rated . . . . . . . . . . . . . . . . . . . . . . . . . 29 tv-ma-l-rated . . . . . . . . . . . . . . . . . . . . . 31 tv-ma-rated . . . . . . . . . . . . . . . . . . . . . . . 29 tv-ma-s-rated . . . . . . . . . . . . . . . . . . . . . . 30 tv-ma-v-rated . . . . . . . . . . . . . . . . . . . . . 30 tv-none-rated . . . . . . . . . . . . . . . . . . . . . 29 tv-pg-d-rated . . . . . . . . . . . . . . . . . . . . . . 31 tv-pg-l-rated . . . . . . . . . . . . . . . . . . . . . . 31 tv-pg-rated . . . . . . . . . . . . . . . . . . . . . . . . 29 tv-pg-s-rated . . . . . . . . . . . . . . . . . . . . . . 30 tv-pg-v-rated . . . . . . . . . . . . . . . . . . . . . . 30 tvs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 tv-y7-fv-rated . . . . . . . . . . . . . . . . . . . . . 30 tv-y7-rated . . . . . . . . . . . . . . . . . . . . . . . . 29 tv-y-rated . . . . . . . . . . . . . . . . . . . . . . . . . 29 v vbi data processing . . . . . . . . . . . . . . . . . . 16 vbi line . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 v-chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 vco gain . . . . . . . . . . . . . . . . . . . . . . . . . . 47 vco lock . . . . . . . . . . . . . . . . . . . . . . . . . . 17 v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 vertical blanking interval (vbi) . . . . . . . . . . 9 video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 video input signal processing . . . . . . . . . . . . . 10 lock mode . . . . . . . . . . . . . . . . . . . . 42, 48 standard . . . . . . . . . . . . . . . . . . . . . . . . . 17 violence blocking . . . . . . . . . . . . . . . . . . . . . 9 voltage/current reference . . . . . . . . . . . . . 11 voltage-controlled oscillator (vco) . . . . . 10 v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 v ss (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 w wovr . . . . . . . . . . . . . . . . . . . . . . . . . . 25 , 39 write . . . . . . . . 11 , 13 , 18 - 20 , 23 - 24 , 35 , 38 addressing . . . . . . . . . . . . . . . . . . . . . . . . 11 sequence . . . . . . . . . . . . . . . . . . . . . . 11 , 20 writing to the i 2 c bus . . . . . . . . . . . . . . . . 19 writing to the z86230 . . . . . . . . . . . . . . . . 24 wrxx . . . . . . . . . . . . . . . . . . . . . . . . . . 24 , 38 x xds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 , 35 activity . . . . . . . . . . . . . . . . . . . . . . . . . . 27 class and type . . . . . . . . . . . . . . . . . . . . . 36 content advisory packet . . . . . . . . . . . . . 9 data . . . . . . . . . . . . . . . 9 - 10 , 16 , 26 - 27 , 36 data activity . . . . . . . . . . . . . . . . . . . . . 39 data activity register . . . . . . . . . . . . . . 26 data output . . . . . . . . . . . . . . . . . . . . . . 17 data packets . . . . . . . . . . . . . . . . . . . . 9 , 36 data recovery . . . . . . . . . . . . 24 , 27 , 35, 44 data stream . . . . . . . . . . . . . . . . . . . . . . . 36 decoding . . . . . . . . . . . . . . . . . . . . . . . . . 35 filter . . . . . . . . . . . . . . . . . . . . .9, 36-37, 39 filter command . . . . . . . . . . . . . . . . . . . . 44 filter register . . . . . . . . . . . . . . . 24 , 35 - 37 filter register script files . . . . . . . . . . . 45 filtering . . . . . . . . . . . . . . . . . . . . . . . . . . 35 network name and call letter data . . . . 20 packets . . . . . . . . . . . . . . . . . . . . . . . . . . 36 program name data . . . . . . . . . . . . . . . . 20 recovery . . . . . . . . . . . . . . . . . . . . . . . . . 26 xdscap . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 xdscap program . . . . . . . . . . . . . . . . . . . 44 xin input . . . . . . . . . . . . . . . . . . . . . . . . . . 48 xout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 x-rated . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 ps000401-tvc0699 z86230?preliminary 61 xtal . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 , 48 circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 mode . . . . . . . . . . . . . . . . . . . . . . . . . 14 , 50 output . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 z z86230 feature set . . . . . . . . . . . . . . . . . . . 16 z86230 output registers . . . . . . . . . . . . . . . 21 z86230 reference circuit . . . . . . . . . . .50 - 52 z86230 register address . . . . . . . . . . . . 24 , 38 z86230 write commands . . . . . . . . . . . . 35 |
Price & Availability of Z8623012SSG
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